Referring now to FIG. 1, a system controller 10 is shown in communication with a CPU 12 and a double data rate (DDR) memory 14. The system controller 10 has a CPU interface module 16 that provides an interface between the CPU 12 an internal bus 18. The system controller 10 also has a DDR memory control module 20 that provides an interface between the internal bus 18 and the DDR memory 14.
Turning now to FIG. 2, signals transmitted between the DDR memory control module 20 and the DDR memory 14 are shown. An address bus ADDR carries address bus signals ADDR0-ADDRN from the DDR memory control module 20 to the DDR memory 14. A control bus CTRL carries control signals RASn, CASn, WEn, and CSn from the DDR memory control module 20 to the DDR memory 14. A clock generated by the DDR memory control module 20 is communicated to the DDR memory 14 by a differential clock signal CLK/CLKN.
A bidirectional data bus DQ is connected between the DDR memory control module 20 and the DDR memory 14. The bidirectional data bus DQ carries data bits DQ0-DQM. A bidirectional data strobe signal (DQS) can be driven either by the DDR memory control module 20 when it is writing data to the DDR memory 14 or by the DDR memory 14 when its data is being read by the DDR memory control module 20. The DDR memory control module 20 generates a data mask (DM) signal. The DM signal masks writing to specified bytes during write transactions from the DDR memory controller 20 to the DDR memory 14. The data strobe signal DQS is tri-stated between the read and write operations of the DDR memory control module 20. While the data strobe signal DQS is tri-stated, it may be undesirably influenced by neighboring signals and oscillate or float to a logic low or logic high state.
During normal operation, the DDR memory control module 20 uses leading and/or trailing edges of the data strobe signal DQS to latch incoming data that appears on the data bus DQ during read cycles. However, if the data strobe signal DQS becomes noisy while it is tri-stated, the DDR memory control module 10 may misinterpret the noise as a valid leading or trailing edge and undesirably latch invalid data from the data bus DQ.